Black reference pixel for backside illuminated image sensor

ABSTRACT

An imaging sensor pixel array includes a semiconductor substrate, a plurality of active pixels and at least one black reference pixel. The plurality of active pixels are disposed in the semiconductor substrate for capturing an image. Each of the active pixels includes a first region for receiving light including a p-n junction for accumulating an image charge and active pixel circuitry coupled to the first region to readout the image charge. The black reference pixel is also disposed within the semiconductor substrate for generating a black level reference value. The black reference pixel includes a second region for receiving light without a p-n junction and black pixel circuitry coupled to the photodiode region without the p-n junction to readout a black level reference signal.

TECHNICAL FIELD

This disclosure relates generally to image sensors, and in particularbut not exclusively, relates to backside illuminated CMOS image sensors.

BACKGROUND INFORMATION

Modern complementary metal-oxide-semiconductor (“CMOS”) imagers ofteninclude some sort of feedback loop to automatically set the black levelin the output. The analog voltage associated with true black may beobtained by reading “black reference pixels.” Black reference pixels aretypically arrayed immediately next to the active image array. Infrontside illuminated (“FSI”) image sensors, one of the metal layerswithin the frontside metal stack shields the reference pixels in orderto block any incoming light. Circuitry within the FSI image sensor thensets the voltage output for the active pixels with reference to theoutput value from these black reference pixels. The black referencepixels are used to generate a low count value or a user specified setpoint value that will typically be displayed as black. Cameras aretraditionally setup to a black level set point that is slightly greaterthan the read noise. Camera gain is then set to achieve a suitableimage. Setting the proper black level is particularly important whenworking at very low signal levels or low ambient light environments. Ifthe black level is set too low, dim objects will be clipped and notdisplayed. If the black level is set too high, image contrast willsuffer.

FIG. 1A illustrates a conventional active pixel 100 of a FSI imagesensor, while FIG. 1B illustrates a conventional black reference pixel105 of a FSI image sensor. The frontside of imaging pixels 100 or 105 isthe side of substrate 110 upon which the pixel circuitry is disposed andover which metal stack 115 for redistributing signals is formed. Inactive pixel 100, the metal layers (e.g., metal layer M1 and M2) arepatterned in such a manner as to create an optical passage through whichlight incident on the frontside of active pixel 100 can reach thephotosensitive photodiode (“PD”) region 120. In contrast, the opticalpassage of black reference pixel 105 is intentionally blocked andcovered over with a metal layer M3.

When FSI image sensors are thinned via traditional methods, the backs ofthe black level reference pixels are exposed, as are the pixels in theactive imaging array. Consequently, light and electrons incident uponthe back of the die may induce signal noise in black reference pixel105, thereby voiding its value as a black reference pixel. In order toregain the benefit of black reference pixels on backside thinned FSIimage sensors, die shielding of incident electrons (or photons) is oftenused. One approach to such shielding is to deposit a metal layer overthe backside of black reference pixel 105, as typically used on thefront side. However, in order to maintain a low dark current either aspecial metalization is required for this backside metal layer or adopant profile must be specified on the backside surface before themetal is deposited. In either case, this additional backside processingrequires significant additional processes. This additional processingmay involve a photolithography step to define the deposition area. Theadded masking and handling associated with photolithography can damagethe sensitive frontside surface, thereby reducing yields.

BRIEF DESCRIPTION OF THE DRAWINGS

Non-limiting and non-exhaustive embodiments of the invention aredescribed with reference to the following figures, wherein likereference numerals refer to like parts throughout the various viewsunless otherwise specified.

FIG. 1A is a cross-sectional view of a conventional frontsideilluminated (“FSI”) active pixel.

FIG. 1B is a cross-sectional view of a conventional FSI black referencepixel.

FIG. 2 is a block diagram illustrating a backside illuminated (“BSI”)imaging system including black reference pixels, in accordance with anembodiment of the invention.

FIG. 3 is a circuit diagram illustrating pixel circuitry of two 4Tpixels within a BSI imaging system, in accordance with an embodiment ofthe invention.

FIG. 4 is a hybrid cross-sectional/circuit illustration of a BSI activepixel, in accordance with an embodiment of the invention.

FIG. 5 is a hybrid cross-sectional/circuit illustration of a BSI blackreference pixel on a P-type epitaxial substrate layer, in accordancewith an embodiment of the invention.

FIG. 6 is a hybrid cross-sectional/circuit illustrating of a BSI blackreference pixel on an N-type epitaxial substrate layer, in accordancewith an embodiment of the invention.

FIG. 7 is a flow chart illustrating a process for operating a BSIimaging system with black reference pixels, in accordance with anembodiment of the invention.

DETAILED DESCRIPTION

Embodiments of a system and method of operation for a backsideilluminated (“BSI”) imaging system with black reference pixels aredescribed herein. In the following description numerous specific detailsare set forth to provide a thorough understanding of the embodiments.One skilled in the relevant art will recognize, however, that thetechniques described herein can be practiced without one or more of thespecific details, or with other methods, components, materials, etc. Inother instances, well-known structures, materials, or operations are notshown or described in detail to avoid obscuring certain aspects.

Reference throughout this specification to “one embodiment” or “anembodiment” means that a particular feature, structure, orcharacteristic described in connection with the embodiment is includedin at least one embodiment of the present invention. Thus, theappearances of the phrases “in one embodiment” or “in an embodiment” invarious places throughout this specification are not necessarily allreferring to the same embodiment. Furthermore, the particular features,structures, or characteristics may be combined in any suitable manner inone or more embodiments.

FIG. 2 is a block diagram illustrating a BSI imaging system 200, inaccordance with an embodiment of the invention. The illustratedembodiment of BSI imaging system 200 includes a pixel array 205, readoutcircuitry 210, function logic 215, and control circuitry 220.

Pixel array 205 is a two-dimensional (“2D”) array of BSI imaging sensorsor active pixels (e.g., AP1, AP2 . . . , APn) and black reference pixels(e.g., BP0, BP1 . . . BP9). In one embodiment, each active pixel is anactive pixel sensor (“APS”), such as a complementarymetal-oxide-semiconductor (“CMOS”) imaging pixel. In one embodiment,black reference pixels include similar or identical structure to theiractive pixel counterparts with the exception that their photodioderegion lacks a p-n junction.

As illustrated, each active pixel is arranged into a row (e.g., rows R1to Ry) and a column (e.g., column C1 to Cx) to acquire image data of aperson, place, or object, which can then be used to render a 2D image ofthe person, place, or object. Pixel array 205 includes one or more blackreference pixels for outputting a black reference signal that may beused to calibrate a black level set point of the active pixels. In theillustrated embodiment, pixel array 205 includes black reference pixelsBP0-BP9 aligned in a single column down the center of pixel array 205.In this case, each black reference pixel may be used to calibrate theactive pixels within its row. Accordingly, each black reference pixel islogically grouped with one or more active pixels to calibrate the blacklevel set point of its associated active pixels. Since many of theinfluences on the black level set point of each active pixel havelocalized variations, it may be desirable to distribute the blackreference pixels throughout pixel array 205 to account for theselocalized variations. Some of these localized influences may includetemperature, parasitic capacitances, structural design differences,lattice structure defects, and the like. Consequently, pixel array 205may include any number of black reference pixels distributed throughoutpixel array 205 in a variety of different patterns (e.g., around theperimeter, in one or more columns, in one or more rows, in one or moreclusters, in a checkerboard pattern, in an irregular distribution, orotherwise).

After each active pixel has acquired its image data or image charge, theimage data is readout by readout circuitry 210 and transferred tofunction logic 215. Readout circuitry 210 may include amplificationcircuitry, analog-to-digital conversion circuitry, or otherwise. In oneembodiment, readout circuitry 210 includes black level referencecircuitry 225 for adjusting or calibrating the black level set point ofeach active pixel. The black level set point is the signal level outputfrom each active pixel at which the pixel is deemed to have captured ablack image. Black level reference circuitry 225 sets the voltage outputfor each of the active pixels with reference to the output value fromits corresponding black reference pixel. The black reference pixelsgenerate a low count value or a user specified set point value that willtypically be displayed as black. Cameras are traditionally setup to ablack level set point that is slightly greater than the read noise. Ifthe black level set point is set too low, dim objects will be clippedand not displayed. If the black level set point is set too high, imagecontrast will suffer.

In one embodiment, readout circuitry 210 may readout a row of image dataat a time along readout column lines (illustrated) or may readout theimage data using a variety of other techniques (not illustrated), suchas a serial readout or a full parallel readout of all pixelssimultaneously. Once read out, function logic 215 may simply store theimage data or even manipulate it by applying post image effects (e.g.,crop, rotate, remove red eye, adjust brightness, adjust contrast, orotherwise).

Control circuitry 220 is coupled to pixel array 205 to controloperational characteristic of pixel array 205. For example, controlcircuitry 220 may generate a shutter signal for controlling imageacquisition. In one embodiment, the shutter signal is a global shuttersignal for simultaneously enabling all pixels within pixel array 205 tosimultaneously capture their respective image data during a singleacquisition window. In an alternative embodiment, the shutter signal isa rolling shutter signal whereby each row, column, or group of pixels issequentially enabled during consecutive acquisition windows.

FIG. 3 is a circuit diagram illustrating pixel circuitry 300 of twofour-transistor (“4T”) active pixels within a BSI imaging array, inaccordance with an embodiment of the invention. Pixel circuitry 300 isone possible pixel circuitry architecture for implementing each activepixel within pixel array 200 of FIG. 2. However, it should beappreciated that embodiments of the present invention are not limited to4T pixel architectures; rather, one of ordinary skill in the art havingthe benefit of the instant disclosure will understand that the presentteachings are also applicable to 3T designs, 5T designs, and variousother pixel architectures.

In FIG. 3, pixels Pa and Pb are arranged in two rows and one column. Theillustrated embodiment of each pixel circuitry 300 includes a photodiodePD, a transfer transistor T1, a reset transistor T2, a source-follower(“SF”) transistor T3, and a select transistor T4. During operation,transfer transistor T1 receives a transfer signal TX, which transfersthe charge accumulated in photodiode PD to a floating diffusion node FD.

Reset transistor T2 is coupled between a power rail VDD and the floatingdiffusion node FD to reset (e.g., discharge or charge the FD to a presetvoltage) under control of a reset signal RST. The floating diffusionnode FD is coupled to control the gate of SF transistor T3. SFtransistor T3 is coupled between the power rail VDD and selecttransistor T4. SF transistor T3 operates as a source-follower providinga high impedance output from the pixel. Finally, select transistor T4selectively couples the output of pixel circuitry 300 to the readoutcolumn line under control of a select signal SEL.

FIG. 4 is a hybrid cross sectional/circuit illustration of a BSI activepixel 400, in accordance with an embodiment of the invention. Activepixel 400 is one possible implementation of active pixels AP1 to APnwithin pixel array 205. The illustrated embodiment of active pixel 400includes a substrate 405, a color filter 410, a microlens 415, a PDregion 421 including a doped PD 420 and a doped interlinking diffusionregion 425, pixel circuitry layers 435, and a metal stack 440. Theillustrated embodiment of pixel circuitry layers 435 include a 4T pixel(other pixel designs may be substituted) disposed over a diffusion well445. A floating diffusion 450 is disposed within diffusion well 445 andcoupled to transfer transistor T1, reset transistor T2, and the gate ofSF transistor T3. The illustrated embodiment of metal stack 440 includestwo metal layers M1 and M2 separated by intermetal dielectric layers 441and 443. Although FIG. 4 illustrates only a two layer metal stack, metalstack 440 may include more or less layers (e.g., three metal layers) forrouting signals over the frontside of pixel array 205. In oneembodiment, a passivation or pinning layer 470 is disposed overinterlinking diffusion region 425. Finally, shallow trench isolations(“STI”) insulate active pixel 400 from adjacent pixels (notillustrated).

As illustrated, imaging pixel 400 is photosensitive to light 480incident on the backside of its semiconductor die. Floating diffusion450 is doped with an opposite conductivity type dopant as diffusion well445 to generate a p-n junction within diffusion well 445 and therebyelectrically isolating floating diffusion 450. Similarly, photodiode 420is doped to form a p-n junction with the surrounding epitaxial layer toaccumulate image charges in response to light 480. In one embodiment,substrate 405 and/or the epitaxial layers formed thereon are doped withP-type dopants. In this case, substrate 405 and the epitaxial layersgrown thereon may be referred to as a P-substrate. In a P-substrateembodiment, diffusion well 445 is a P+ well implant, while PD 420,interlinking diffusion region 425, and floating diffusion 450 are N-typedoped. In an embodiment where substrate 405 and/or the epitaxial layersthereon are N-type, diffusion well 445 is also N-type doped, while PD420, interlinking diffusion region 425, and floating diffusion 450 havean opposite P-type conductivity.

FIG. 5 is a hybrid cross-sectional/circuit illustration of a BSI blackreference pixel 500, in accordance with an embodiment of the invention.Black reference pixel 500 is formed on a P-type epitaxial/substrate 505and the pixel circuitry (e.g., transfer transistor T1) implemented withNMOS transistors over a P-well (diffusion well 445). In one embodiment,black reference pixel 500 is similar to active pixel 400, except PDregion 521 is undoped with N-type dopants. As such, PD region 521retains the same doping characteristic as the surrounding epitaxialsemiconductor material (i.e., P-type). Since PD region 521 is not dopedwith N-type dopants, a p-n junction is not generated and a photodiode isnot formed. Accordingly, the structure of black reference pixel 500 isnonresponsive to light 480 since its active region has been removed.However, the backside has not been covered with a metal layer to blockout light 480. Rather, the optical path from microlens 415 to PD region521 is still penetrable by light 480. By rendering black reference pixel400 insensitive to light, depositing a blocking metal layer on thebackside of the die can be avoided.

Since the pixel circuitry within pixel circuitry layers 435 is retained,black reference pixel 500 generates a baseline or black level referencesignal from which the photosensitive active pixel 400 can be calibratedto offset or cancel out the non-optically generated portion of itsoutput signal. With the optically sensitive portion (e.g., PD 420 andinterlinking diffusion region 425) of black reference pixel 500 removed,photo-generated carriers are not created within PD region 521.Therefore, any signal generated by black reference pixel 500 is thecombination of one or more leakage signals, thermally generated signals,or other unwanted signals. By keeping the remaining aspects (e.g., pixelsize, pixel circuitry, etc.) of black reference pixel 500 as similar aspossible to active pixel 400, these unwanted signal components generatedby black reference pixel 500 will closely match or approximate theunwanted signal components generated by active pixel 400. However, itshould be appreciated that embodiments of the present invention maystill work within acceptable tolerances if other deviations betweenblack reference pixel 500 and active pixel 400 are permitted. Forexample, in one embodiment, pinning layer 470 may also be removed.

FIG. 6 is a hybrid cross-sectional/circuit illustration of a BSI blackreference pixel 600, in accordance with an embodiment of the invention.Black reference pixel 600 is formed on an N-type epitaxial/substrate 605and the pixel circuitry (e.g., transfer transistor T1) implemented withPMOS transistors over an N-well (diffusion well 445). Black referencepixel 600 is similar to black reference pixel 500, except the dopingconductivity types (i.e., p-type dopants and n-type dopants) arereversed. PD region 621 is undoped with P-type dopants. As such, PDregion 521 retains the same doping characteristic as the surroundingepitaxial semiconductor material (i.e., N-type). Since PD region 621 isnot doped with P-type dopants, a p-n junction is not generated and aphotodiode is not formed. Accordingly, black reference pixel 600 isnonresponsive to light 480 since its active region has been removed.

FIG. 7 is a flow chart illustrating a process 700 for operating BSIimaging system 200 with black reference pixels (e.g., black referencepixels 500 or 600), in accordance with an embodiment of the invention.The order in which some or all of the process blocks appear in process700 should not be deemed limiting. Rather, one of ordinary skill in theart having the benefit of the present disclosure will understand thatsome of the process blocks may be executed in a variety of orders notillustrated.

In a process block 700, the active pixels of pixel array 205 are reset.Depending upon whether a rolling or global shutter is used some or allactive pixels may be reset at a time. Resetting the active pixelsincludes discharging or charging PD 420 to a predetermined voltagepotential, such as VDD. The reset is achieved by asserting both the RSTsignal to enable reset transistor T2 and asserting the TX signal toenable transfer transistor T1. Enabling T1 and T2 couples PD 420 andfloating diffusion 450 to power rail VDD.

Once reset, the RST signal and the TX signal are de-asserted to commenceimage acquisition by photodiode 420 (process block 710). Light 480incident on the backside of an active pixel 400 is focused by microlens415 through color filter 410 onto the backside of PD 420. Color filter410 operates to filter the incident light 480 into component colors(e.g., using a Bayer filter mosaic or color filter array). The incidentphotons cause charge to accumulate within the diffusion region of thephotodiode.

Once the image acquisition window has expired, the accumulated chargewithin PD 420 is transferred via the transfer transistor T1 to floatingdiffusion 450 for readout. In some embodiments, a storage capacitor maybe coupled to floating diffusion 450 to temporarily store the imagecharge. In a process block 715, the SEL signal is asserted to transferthe image data onto the readout column for output to the function logic215 via readout circuitry 210. It should be appreciated that readout mayoccur on a per row basis via column lines (illustrated), on a per columnbasis via row lines (not illustrated), on a per pixel basis (notillustrated), or by other logical groupings.

At the same time that the image data is read out from the active pixels,black level reference signal(s) are readout from the black referencepixels (e.g., BP0 through BP9). Each black reference pixel is logicallyassociated with a portion of the active pixels and its black levelreference signal used to offset or configure the black level set pointof its associated active pixels.

The processes explained above are described in terms of computersoftware and hardware. The techniques described may constitutemachine-executable instructions embodied within a machine (e.g.,computer) readable storage medium, that when executed by a machine willcause the machine to perform the operations described. Additionally, theprocesses may be embodied within hardware, such as an applicationspecific integrated circuit (“ASIC”) or the like.

A machine-readable storage medium includes any mechanism that provides(i.e., stores) information in a form accessible by a machine (e.g., acomputer, network device, personal digital assistant, manufacturingtool, any device with a set of one or more processors, etc.). Forexample, a machine-readable storage medium includesrecordable/non-recordable media (e.g., read only memory (ROM), randomaccess memory (RAM), magnetic disk storage media, optical storage media,flash memory devices, etc.).

The above description of illustrated embodiments of the invention,including what is described in the Abstract, is not intended to beexhaustive or to limit the invention to the precise forms disclosed.While specific embodiments of, and examples for, the invention aredescribed herein for illustrative purposes, various modifications arepossible within the scope of the invention, as those skilled in therelevant art will recognize.

These modifications can be made to the invention in light of the abovedetailed description. The terms used in the following claims should notbe construed to limit the invention to the specific embodimentsdisclosed in the specification. Rather, the scope of the invention is tobe determined entirely by the following claims, which are to beconstrued in accordance with established doctrines of claiminterpretation.

What is claimed is:
 1. An imaging sensor pixel array, comprising: asemiconductor substrate; a plurality of active pixels disposed in thesemiconductor substrate for capturing an image, each of the activepixels including a first region for receiving light including a p-njunction for accumulating an image charge and active pixel circuitrycoupled to the first region to readout the image charge; and at leastone black reference pixel disposed within the semiconductor substratefor generating a black level reference value that includes effects dueto dark current within the imaging sensor pixel array without shieldingthe light from reaching the at least one black reference pixel, theblack reference pixel including a second region for receiving lightwithout a p-n junction and black pixel circuitry coupled to the secondregion without the p-n junction to readout a black level referencesignal, wherein the black reference pixel does not include a shieldinglayer disposed on a light incident side of the imaging sensor pixelarray that is positioned to block the light from reaching the secondregion of the black reference pixel, wherein the black pixel circuitryincludes a transfer transistor coupled to the second region such thatthe black level reference value includes effects due to dark currentwithin the transfer transistor of the black pixel circuitry.
 2. Theimaging sensor pixel array of claim 1, wherein the second region of theblack reference pixel is either undoped or doped to have only oneconductivity type and nonresponsive to incident light.
 3. The imagingsensor pixel array of claim 2, wherein the imaging sensor pixel arraycomprises a backside illuminated complementary metal-oxide-semiconductor(“CMOS”) array.
 4. The imaging sensor pixel array of claim 3, whereinthe backside illuminated CMOS array does not include a metal layerdisposed on a backside of the imaging sensor pixel array to block lightfrom reaching the black reference pixel.
 5. The imaging sensor pixelarray of claim 3, further comprising: a metal stack disposed on afrontside of the backside illuminated CMOS array for routing signalsfrom the active pixels and the at least one black reference pixel; andan array of microlenses disposed on a backside of the backsideilluminated CMOS array for focusing light onto the first region of eachof the active pixels.
 6. The imaging sensor pixel array of claim 1,wherein the black pixel circuitry is identical to the active pixelcircuitry.
 7. The imaging sensor pixel array of claim 6, wherein theblack pixel circuitry and the active pixel circuitry each comprise: atransfer transistor coupled between the first or second region and afloating diffusion; a reset transistor coupled to the floatingdiffusion; a source-follower transistor coupled to the floatingdiffusion to output the image charge or the black level referencesignal; and a select transistor to select the pixel from other pixelsfor readout.
 8. A method of operation of a backside illuminated pixelarray, comprising: exposing a plurality of active pixels and at leastone black reference pixel to light incident upon a backside of theactive and black reference pixels; capturing image data within theactive pixels in response to the light, wherein the black referencepixel is nonresponsive to the light; reading out the image data from theactive pixels; and reading out at least one black level reference signalfrom the at least one black reference pixel, the black level referencesignal including effects due to dark current within the backsideilluminated pixel array without shielding the light from reaching the atleast one black reference pixel, wherein exposing the black referencepixel to light comprises permitting the light to enter the backside ofthe black reference pixel by not blocking the light from the blackreference pixel with a light shielding layer disposed on the backside ofthe black reference pixel, wherein the black reference pixel includesblack pixel circuitry that includes the same circuit elements as activepixel circuitry of each of the active pixels, wherein the black pixelcircuitry includes a transfer transistor such that the black levelreference signal includes effects due to dark current within thetransfer transistor of the black pixel circuitry.
 9. The method of claim8, further comprising adjusting a black level of the active pixels withreference to the black level reference signal from the black referencepixel.
 10. The method of claim 8, wherein the backside illuminated pixelarray comprises a complementary metal-oxide-semiconductor (“CMOS”) pixelarray.
 11. The method of claim 8, wherein reading out the at least oneblack level reference signal comprises reading out a thermally generatedsignal from the black level reference signal using pixel circuitrydisposed within the black level reference signal.
 12. The method ofclaim 11, wherein the black reference pixel includes a first region forreceiving the light that is either undoped or doped to have only oneconductivity type and nonresponsive to the light, wherein the activepixels each include a doped photodiode region having a p-n junction foraccumulating an image charge in response to the light.
 13. An imagingsystem, comprising: a backside illuminated array of imaging pixelsincluding: a plurality of active pixels to capture image signals inresponse to light incident on a backside of the array; and at least oneblack reference pixel for generating a black level reference signal thatincludes effects due to dark current within the backside illuminatedarray of imaging pixels without shielding the light from reaching the atleast one black reference pixel, a backside of the black reference pixelpenetrable by the light but the black reference pixel having anonresponsive structure to the light, wherein the backside of the blackreference pixel is not covered over with a light shield; readoutcircuitry coupled to the backside illuminated array of imaging pixels toreadout the image signal and the black level signal; and referencecircuitry coupled to receive the black level signal and to adjust ablack level set point of the active pixels based at least in part on theblack level signal, wherein the black reference pixel includes blackpixel circuitry includes the same circuit elements as active pixelcircuitry of each of the active pixels, wherein the black pixelcircuitry includes a transfer transistor such that the black levelreference signal includes effects due to dark current within thetransfer transistor of the black pixel circuitry.
 14. The imaging systemof claim 13, wherein the black reference pixel does not include aphotodiode.
 15. The imaging system of claim 14, wherein the blackreference pixel includes black pixel circuitry similar to active pixelcircuitry included within each of the active pixels, the black pixelcircuitry configured to readout a thermally generated signal as theblack level reference signal.
 16. The imaging system of claim 13,wherein the array of imaging pixels comprises a plurality of blackreference pixels dispersed about the array, wherein each of the blackreferences pixels is logically associated with a subset of the activepixels for adjusting the black level set point of the associated activepixels.
 17. The imaging system of claim 13, wherein the array of imagingpixels comprises an array of complementary metal-oxide-semiconductor(“CMOS”) imaging sensors.
 18. The imaging system of claim 17, whereinthe backside illuminated array of imaging pixels further includes: ametal stack disposed on a frontside of the array for routing signalsfrom the active pixels and the at least one black reference pixel; andan array of microlenses disposed on the backside of the array forfocusing light onto a doped photodiode region of each of the activepixels.
 19. The imaging system of claim 13, wherein the backside of theblack reference pixel is not covered over with a metal layer.